Vintage Computing 65F02

The 100 MHz 6502

The 6502 was the CPU in my first computer (an Apple II plus), as well as many other popular home computers of the late 1970s and 80s. It lived on well into the 1990s in game consoles and chess computers, mostly in its updated “65C02” CMOS version. Here’s a re-implementation of the 65C02 in an FPGA, in a pin-compatible format that lets you upgrade those old computers and games to 100 MHz clock rate!

The concept

The idea of implementing a CPU core inside an FPGA is not new, of course. In fact, the CPU core I am using is not my own, but was developed as a 6502 core by Arlet Ottens, and extended to cover the 65C02 opcodes by Ed Spittles and David Banks. A big thank-you to Arlet, Ed, and Dave for developing the core and sharing it freely! Links to their original work are on the Files & Links page.

I packaged this in a Spartan-6 FPGA (with 64 kByte on-chip RAM), on a small circuit board which is just the size of a 40-pin dual inline package, with pins matching the 65C02 pinout. I added logic inside the FPGA which can access the external 65C02 bus with the correct timing, based on whatever clock is coming in from the host system. Inside the FPGA, the CPU core runs at 100 MHz. I dubbed this the “65F02”, where the “F” might stand for FPGA or for “Fast”. ;-)

65F02 circuit board

The 65F02 circuit board – same footprint and pinout as the original 6502 and 65C02 CPU.

The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. Then the CPU gets going, using the internal memory at 100 MHz for all bus accesses except for any I/O addresses – for these, the internal CPU pauses, and an external bus cycle is started at whatever the external clock speed is.

Kudos to Roland Langfeld, who suggested this elegant way of integrating an accelerator into almost any host, and has contributed a lot during the testing and debugging effort. Roland’s original interest was in 6502-based chess computers (there were some really nice ones in the 1980s). But we have successfully tested the prototype 65F02s in an Apple II and a Commodore 8032, as well as various chess computers.

65F02 prototype with logic analyzer probes

Thanks go to Roland Langfeld – for the idea for the 65F02 and many hours of debugging and testing in Mephisto chess computers and the Commodore 8032.

65F02 installed in Mephisto Milano chess computer

The first compact 65F02 installed in a Mephisto Milano chess computer. The populated circuit board is less than a millimeter higher than the original chip package, hence also fits into tight enclosures.

Supported host systems

Chess computers

We have focused on Mephisto chess computers first, since these are at the center of Roland’s collector’s interest. But many others are on the wishlist, including Fidelity (Elite A/S Budapest and Glasgow, Prestige, Avantgarde), Novag (Super Constellation, Super Expert C), Chafitz (ARB 4.0, Sargon, Steinitz), SciSys (Turbostar), …

Microcomputers

So far, we are supporting the two 6502-based members of the classic 1977 “Trinity” of home computers – the Apple II and the Commodore PET series. It may be possible and worthwhile to also support some slightly later machines: The Acorn BBC Micro, Atari 400 and 800, and maybe the Commodore C64 come to mind. I don’t have any of these computers though. Please contact me if you are interested to help with an adaptation of the 65F02!

A caveat is in order here. The home computers, with their flexibility and expandability on both the hardware and software side, are bound to encounter limitations and incompatibilities:

Memory expansion boards and bank switching need to be known to the 65F02 in order to work at all, and since the 65F02 only has 64 kByte of RAM on board, it cannot fully accelerate the extended memory. Also, while the 65F02 makes an effort to detect the access to time-critical peripheral devices, and switch back to the original slow speed temporarily, there will probably be incompatible software or add-on hardware. And finally, some software you simply don’t want to be accelerated – try an action video game at 100 MHz to understand that concern…

I am currently thinking about the best way to give users control over the acceleration when using the 65F02 in microcomputers: Should it be a “poke” to a memory address which is unused in the original computer? Should the power-on default setting be “accelerated” or “original speed”? Or is a hardware switch better? Opinions are welcome!

Status and next steps

This is a hobby project, and I have no plans at the moment to take it commercial.

So far, only two of the small-form-factor PCBs have been assembled, and have been successfully tested in the above-mentioned computers. The tested computers include environments with TTL and CMOS logic levels, and clock rates ranging from 1 to 5 MHz. IRQs and NMIs are used in the hosts; some of the Mephisto chess computers actively use the READY signal to slow down the CPU, and the 65F02 respects that nicely. We have not really put the SO (set overflow) input through its paces, but believe it to work.

I am waiting for a slightly revised PCB to arrive, which will offer better support for programming it via USB. In parallel, the additional features discussed on the Details page have been implemented, but not tested yet. I will catch up on that once the revised PCB has been brought up.

Based on the revised PCB, I then plan to hand-assemble a handful of boards and make them available to beta testers. Getting the 65F02 to support additional host systems will be one focus; the chess computer collectors will also be interested in assessing what improvement in playing strength one gets from a 20- to 30-fold increase in the clock rate.

I am not sure yet whether and how to make the 65F02 available to a broader audience. Soldering the BGA of the Spartan-6 FPGA, and also the six small level converter chips, is probably beyond most hobbyists’ reach. So simply open-sourcing the design does not get us very far. I could have the boards made and populated by a PCB assembly service; maybe after taking pre-orders so I can estimate the quantity. But I shy away from the European compliance requirements for selling electronics, and also from the cottage-industry work of testing, configuring and mailing boards. Assessing options…